evaluation
Evaluate an individual IP configuration
Inspect the named release and establish technical fit.
Discuss this scopeGarCompute & AI
THE TECHNICAL ROLE
A clear integration boundary.
Garmo-RV32-EC integration role: CPU — high-efficiency RISC-V MCU core. Documented composition: 2-wide fetch/decode with decoupled branch unit and 16-entry return stack; Physical memory protection, machine/user modes, optional MMU-lite; 32/64 KiB I/D cache options or deterministic TCM.
01
2-wide fetch/decode with decoupled branch unit and 16-entry return stack
02
Physical memory protection, machine/user modes, optional MMU-lite
03
32/64 KiB I/D cache options or deterministic TCM
TECHNICAL OVERVIEW
Download the product briefThe details matter.
- Canonical identity
- IP-2071
- Responsibility
- CPU — high-efficiency RISC-V MCU core
- Documented interface architecture
- Harvard I/D memory, AXI/AHB adapter, debug, CLINT/PLIC/AIA option, TCM
- Documented building blocks
- 2-wide fetch/decode with decoupled branch unit and 16-entry return stack; Physical memory protection, machine/user modes, optional MMU-lite; 32/64 KiB I/D cache options or deterministic TCM
- Delivery boundary
- Evaluation / IP scope
- Evidence scope
- Evaluation package
- Architecture targets · not measurements
- RV32IMAFDCB + optional 128-bit V; 2-wide in-order; >6 CoreMark/MHz target; <12-cycle interrupt entry.
Evaluation packageKnow the release.
Know the release.
Know what it establishes.
Canonical technology and its architecture/integration role are recorded. The offered delivery is confirmed against the exact release before licensing.
Source basis: Bible v7.42 IP-2071. This is a controlled-portfolio summary, not a fresh execution of the chip qualification flow.
Release-specific qualification
No node-port, silicon-performance, standards certification or analog qualification is inherited from a related product.
Canonical record: P0 / REPRESENTATIVE ARCHITECTURE RTL — concrete integration specification and synthesizable RTL shell/representative datapath only; all frequency, throughput, power, area, jitter and standards-superiority figures remain architecture targets until the required evidence hierarchy closes.
A PATH THAT FITS THE PROJECT
Build with Garmo-RV32-EC.
Technical scope, rights, support and release configuration are agreed before delivery.
production
Named-design production license
Agree deployment or design rights, deliverables and support.
Discuss this scopecustom
Node binding or derivative integration
Define the customer-specific work and acceptance criteria.
Discuss this scopeKeep exploring.
Compute & AI
NPJ SolveTile v1.0.0
Reusable solver/bitset/sparse tile binding lane ALU, popcount/zero-skip, descriptor FIFO and deterministic transport to a reference model and SV source.
RTL + modelsIP-4276 · Source / reference evidence
Compute & AI
Garmo RISC-V Processor IP
CPU pipeline; cache/memory interfaces; MMU/TLB options; interrupt/debug; FPU/vector options; compiler/software support; verification/formal collateral; hardened physical views.
Architecture IPIP-001 · Source documented
Compute & AI
Garmo-NPU-1024
AI Compute — 1024 tensor-slice cloud/robotics NPU
Evaluation packageIP-2067 · Source documented
Your next big idea.
Let’s build it together.
Start with a chip, a software release or a single IP block.
CANONICAL EVIDENCE RECORD · IP-2071How evidence priority is determined ↗
Source documented
A concrete source or implementation record exists; the selected evidence does not establish complete qualification.
Source: Bible 7.42 VERIFIED V29 · Bible v7.42 IP-2071.
Record integrity and qualification boundary
Retained exact-release source reference; no new table locator was inferred.
Evidence ranking for evaluation prioritization; not a probability or certification.