evaluation
Evaluate an individual IP configuration
Inspect the named release and establish technical fit.
Discuss this scopeMemory & storage
Garmo-SRAM-Compiler
Memory IP — node-adaptable SRAM compiler architecture
Evaluation package
GarMemory & storage
THE TECHNICAL ROLE
A clear integration boundary.
Garmo-SRAM-Compiler integration role: Memory IP — node-adaptable SRAM compiler architecture. Documented composition: Bank/word/bit partition search driven by PPA and aspect-ratio constraints; Redundant row/column repair, MBIST/BISR and SECDED option; Retention, light/deep sleep, power gating and per-bank clock gating.
01
Bank/word/bit partition search driven by PPA and aspect-ratio constraints
02
Redundant row/column repair, MBIST/BISR and SECDED option
03
Retention, light/deep sleep, power gating and per-bank clock gating
TECHNICAL OVERVIEW
Download the product briefThe details matter.
- Canonical identity
- IP-2091
- Responsibility
- Memory IP — node-adaptable SRAM compiler architecture
- Documented interface architecture
- compiler manifest + generated Verilog model/Liberty/LEF/GDS contract; runtime SRAM ports
- Documented building blocks
- Bank/word/bit partition search driven by PPA and aspect-ratio constraints; Redundant row/column repair, MBIST/BISR and SECDED option; Retention, light/deep sleep, power gating and per-bank clock gating
- Delivery boundary
- Evaluation / IP scope
- Evidence scope
- Evaluation package
- Architecture targets · not measurements
- 64 B to 16 MiB generated macros; 1RW/1R1W/2RW families; ECC/repair/retention options.
Evaluation packageKnow the release.
Know the release.
Know what it establishes.
Canonical technology and its architecture/integration role are recorded. The offered delivery is confirmed against the exact release before licensing.
Source basis: Bible v7.42 IP-2091. This is a controlled-portfolio summary, not a fresh execution of the chip qualification flow.
Release-specific qualification
No node-port, silicon-performance, standards certification or analog qualification is inherited from a related product.
Canonical record: P1 / REPRESENTATIVE ARCHITECTURE RTL — concrete integration specification and synthesizable RTL shell/representative datapath only; all frequency, throughput, power, area, jitter and standards-superiority figures remain architecture targets until the required evidence hierarchy closes.
A PATH THAT FITS THE PROJECT
Build with Garmo-SRAM-Compiler.
Technical scope, rights, support and release configuration are agreed before delivery.
production
Named-design production license
Agree deployment or design rights, deliverables and support.
Discuss this scopecustom
Node binding or derivative integration
Define the customer-specific work and acceptance criteria.
Discuss this scopeKeep exploring.
Memory & storage
KENBE 512-bit Compare / Filter Near-Memory
512-bit bounded compare/filter engine.
RTL + modelsIP-4009 · Source / reference evidence
Memory & storage
KENBE 512-bit XOR Reduction Near-Memory
512-bit XOR/reduction datapath for guarded near-memory work.
RTL + modelsIP-4011 · Source / reference evidence
Memory & storage
KENBE Atomic Commit
Controls bounded atomic transaction-group commit/abort.
RTL + modelsIP-4031 · Source / reference evidence
Your next big idea.
Let’s build it together.
Start with a chip, a software release or a single IP block.
CANONICAL EVIDENCE RECORD · IP-2091How evidence priority is determined ↗
Source documented
A concrete source or implementation record exists; the selected evidence does not establish complete qualification.
Source: Bible 7.42 VERIFIED V29 · Bible v7.42 IP-2091.
Record integrity and qualification boundary
Retained exact-release source reference; no new table locator was inferred.
Evidence ranking for evaluation prioritization; not a probability or certification.