KENBE 512-bit Compare / Filter Near-Memory
512-bit bounded compare/filter engine.
RTL + modelsRelated canonical identities, organized together. A shared family is not a claim that every release is mutually compatible or equally qualified.
512-bit bounded compare/filter engine.
RTL + models512-bit XOR/reduction datapath for guarded near-memory work.
RTL + modelsControls bounded atomic transaction-group commit/abort.
RTL + modelsChecks memory request domain/authority permissions.
RTL + modelsRepair/remap map used to redirect defective memory regions/entries.
RTL + modelsGarmo-side CXL memory/fabric adapter boundary; not PHY/compliance IP.
RTL + modelsBoundary/control contract to qualified encryption/authentication macros without toy cryptography.
RTL + modelsGarmo-side DDR controller/PHY boundary adapter.
RTL + modelsStages externally visible effects until atomic commit validation.
RTL + modelsRejects stale epoch/version operations under the KENBE transaction contract.
RTL + modelsEight-lane bounded gather-assist engine.
RTL + modelsGarmo-side HBM channel/base-die boundary adapter.
RTL + modelsTracks access heat for tier-placement/migration policy.
RTL + modelsTracks memory-region health for routing/quarantine/degraded policy.
RTL + modelsControls version-preserving live memory movement across tiers.
RTL + modelsControls patrol scrub/error-maintenance sequencing.
RTL + modelsMaintains commit-group journal/recovery state for persistent operations.
RTL + modelsArbitrates transactions using QoS/deadline policy.
RTL + modelsCommon descriptors, enums, transaction types and family constants.
RTL + models72/64 SECDED decode/correction/detection path.
RTL + models72/64 SECDED encoding path.
RTL + modelsPortable wrapper boundary for real compiled SRAM macro integration.
RTL + modelsRoutes transactions to selected physical/logical memory tiers.
RTL + modelsTracks object/line versions supporting stale-operation rejection and migration invariants.
RTL + modelsManaged LLC/SLC/scratchpad product with QoS/version/isolation/migration hooks.
RTL + modelsType-3/fabric-memory control target with pooling, telemetry, lease/version, isolation and live migration.
RTL + modelsController/scheduler above licensed DDR5/MRDIMM-class PHY with QoS, telemetry and fault containment.
RTL + modelsObject/tier map, migration, telemetry, QoS, commit domains and software policy integration.
RTL + modelsWide-channel HBM control target with scheduling, health routing, integrity metadata and tier migration.
RTL + modelsBounded reductions, gather/scatter assist and compare/filter under common semantic guards.
RTL + modelsJournaled commit groups, persist barriers, write-intent and replay/recovery contracts.
RTL + modelsRepair, scrub, poison, quarantine, lane-sparing hooks and deterministic degraded modes.
RTL + modelsDomain/authority/epoch/version/replay/integrity control with certified crypto macro boundary.
RTL + modelsProtected SRAM product with SECDED, repair, scrub, effect ledger and atomic bundles.
RTL + modelsStart with a chip, a software release or a single IP block.