Keep useful state close

Atomic multi-actuator prepare/validate/commit/fallback engine

Reconstruction-recipe memory controller with integrity gating

Defines a parameterized banked controller that routes MCD-like line operations to independent banks using the proven line-store contract.

Defines ECC, poison, scrub, remap/spare interfaces and media-specific telemetry hooks while keeping silicon retention/disturb/wear claims at foundry/vendor characterization boundaries.

Four-bank P64 controller implementation routing full-line operations among independent production-facing banks rather than the earlier reduced-width controller proof.

Forge named implementation

Production-facing full-width bank integrating P64 data, metadata, access guard, ECC, repair/remap and line operation paths around the controlled SRAM boundary.

Digital RTL implementation indexed as kx_cache_coherency. The recorded role is cache coherency; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_cache_l1. The recorded role is cache l1; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_circular_buffer. The recorded role is circular buffer; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_ddr3_ctrl. The recorded role is ddr3 controller; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_ddr4_ctrl. The recorded role is ddr4 controller; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_data_cache. The recorded role is data cache; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_dcache_nonblock. The recorded role is dcache nonblock; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_ecc_encoder. The recorded role is ecc encoder; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_fifo_async. The recorded role is fifo asynchronous; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_fifo_sync. The recorded role is fifo synchronizer; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_flash_ctrl. The recorded role is flash controller; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_flash_ecc. The recorded role is flash ecc; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_ftl_engine. The recorded role is ftl engine; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_gddr6_ctrl. The recorded role is gddr6 controller; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_hbm_ctrl. The recorded role is hbm controller; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_hbm3_ctrl. The recorded role is hbm3 controller; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_harq_buffer. The recorded role is harq buffer; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_icache_prefetch. The recorded role is icache prefetch; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_instruction_cache. The recorded role is instruction cache; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_lpddr4_ctrl. The recorded role is lpddr4 controller; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_lpddr5_ctrl. The recorded role is lpddr5 controller; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_mmu. The recorded role is mmu; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_memory_bist. The recorded role is memory bist; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_nand_flash_ctrl. The recorded role is nand flash controller; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_nor_flash_ctrl. The recorded role is nor flash controller; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_packet_buffer. The recorded role is packet buffer; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_prefetch_buffer. The recorded role is prefetch buffer; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_queue_fifo. The recorded role is queue fifo; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_riscv_aext. The recorded role is risc-v atomic extension; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_regfile. The recorded role is regfile; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_register_file_2r1w. The recorded role is register file 2r1w; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_rob. The recorded role is reorder buffer; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_ring_buffer. The recorded role is ring buffer; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_sdram_ctrl. The recorded role is sdram controller; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_store_buffer. The recorded role is store buffer; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_tlb. The recorded role is tlb; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_trace_buffer. The recorded role is trace buffer; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_video_line_buffer. The recorded role is video line buffer; exact interfaces, parameters and functional coverage are release-bound.

Digital RTL implementation indexed as kx_wear_leveler. The recorded role is wear leveler; exact interfaces, parameters and functional coverage are release-bound.

Frozen executable bootstrap product containing lexer/parser/checker/interpreter, C11 native/FFI, DSIR, formatter/tests/docs/package lock, bootstrap LSP/memory plan and Bible integration.

512-bit bounded compare/filter engine.

512-bit XOR/reduction datapath for guarded near-memory work.

Controls bounded atomic transaction-group commit/abort.

Repair/remap map used to redirect defective memory regions/entries.

Garmo-side CXL memory/fabric adapter boundary; not PHY/compliance IP.

Garmo-side DDR controller/PHY boundary adapter.

Stages externally visible effects until atomic commit validation.

Eight-lane bounded gather-assist engine.

Garmo-side HBM channel/base-die boundary adapter.

Tracks access heat for tier-placement/migration policy.

Tracks memory-region health for routing/quarantine/degraded policy.

Controls version-preserving live memory movement across tiers.

Controls patrol scrub/error-maintenance sequencing.

Maintains commit-group journal/recovery state for persistent operations.

Arbitrates transactions using QoS/deadline policy.

Common descriptors, enums, transaction types and family constants.

72/64 SECDED decode/correction/detection path.

72/64 SECDED encoding path.

Portable wrapper boundary for real compiled SRAM macro integration.

Routes transactions to selected physical/logical memory tiers.

Tracks object/line versions supporting stale-operation rejection and migration invariants.

Stable SRAM and streaming PHY wrappers isolate KOURAN digital logic from foundry/vendor memory and I/O hard macros so the architecture can target SKY130, N2, 18A-class and package-specific implementations.

Authorizes object access only when permission, domain, epoch and version policy all succeed; failure faults the current neighborhood before ledgered writes become externally visible.

Versioned side metadata communicates execution class, dependency, precision, locality, deadline, security, reproducibility, migration and accelerator-shape intent without replacing the canonical stream.

N-participant prepare/commit/rollback architecture requiring all participating objects to be valid/ready before externally visible commit; distinct from single-address RMW atomics.

Associates architectural version, domain/permissions/epoch, sharing mode, tier/migration state, ECC/poison/scrub, dirty/persistence and QoS/deadline state with each logical line.

Concrete 64-byte / 512-bit VMOL datapath with 576-bit eight-lane SECDED proof-storage path and metadata-coupled control; moves the prior production target into implemented P64 technology.

Integrated digital control plane, tenant/WDM allocation, configuration ownership/epochs, scheduling, fault quarantine, ECC, telemetry, Morph compiler, behavioral PCM/MZI/WDM/thermal models, abstract 128x128 photonic GDS generation and verification/signoff harnesses.

Coherent fabric-memory controller architecture with an explicit protocol and physical-interface boundary.

Memory — high-throughput DDR5 controller

Low-power DRAM controller architecture with scheduling and external PHY integration.

Memory IP — node-adaptable SRAM compiler architecture

Managed LLC/SLC/scratchpad product with QoS/version/isolation/migration hooks.

Type-3/fabric-memory control target with pooling, telemetry, lease/version, isolation and live migration.

Controller/scheduler above licensed DDR5/MRDIMM-class PHY with QoS, telemetry and fault containment.

Object/tier map, migration, telemetry, QoS, commit domains and software policy integration.

Wide-channel HBM control target with scheduling, health routing, integrity metadata and tier migration.

Bounded reductions, gather/scatter assist and compare/filter under common semantic guards.

Repair, scrub, poison, quarantine, lane-sparing hooks and deterministic degraded modes.

Protected SRAM product with SECDED, repair, scrub, effect ledger and atomic bundles.

Compute/memory/I/O/power/fabric/management pod + local bridge/RDL + power/thermal/mechanical interfaces

Directory; snoop filtering; pooling; migration; NUMA; RAS

Versioned memory-service semantics alongside GFI-Lite/Stream/DMA/Event/Trace

Memory attributes, ordering, cacheability, atomics, DMA/coherency, NUMA, ECC, poison, scrub, encryption hooks

Adaptive scheduling; ECC/scrub; health; remap; backend adapters