GSH-130A
Analog socket contract; digital management; calibration firmware path; AMS smoke flow; PEX/LVS/ERC/PVT collateral.
Qualified releaseBreadth and immediate availability are different. These shelves preserve that distinction without promoting underlying qualification.
Strongest currently documented release evidence; exact rights and process scope remain release-specific.
Analog socket contract; digital management; calibration firmware path; AMS smoke flow; PEX/LVS/ERC/PVT collateral.
Qualified releaseDigital user socket; GFI; management; reset isolation; DMA; trace; DFT; GPIO/debug; physical contract.
Qualified releaseGTI/GTG; data, management and lifeboat fabrics; analog service; power/clock/reset; security/RAS; GDI
Controlled physical releaseDigital RTL implementation indexed as kx_4b5b_decoder. The recorded role is 4b5b decoder; exact interfaces, parameters and functional coverage are release-bound.
Internal physical evidenceDigital RTL implementation indexed as kx_4b5b_encoder. The recorded role is 4b5b encoder; exact interfaces, parameters and functional coverage are release-bound.
Internal physical evidenceDigital RTL implementation indexed as kx_aes_engine. The recorded role is aes engine; exact interfaces, parameters and functional coverage are release-bound.
Internal physical evidenceImplemented evidence supports technical evaluation; physical/foundry qualification is not inferred.
Chiplet admission, quarantine and trust-boundary engine
Executed digital evidenceConsequence-class tag propagation and reliability policy fabric
Executed digital evidenceLive silicon characterization/model-store/VF constraint deliverable
Executed digital evidenceAtomic multi-actuator prepare/validate/commit/fallback engine
Executed digital evidenceReconstruction-recipe memory controller with integrity gating
Executed digital evidenceChecks requesting domain, read/write permission masks and revocation epoch at the point where memory work is accepted.
Executed digital evidenceMeaningful implementation or engineering evidence exists, with additional closure or qualification gates remaining.
Distinct TDB-oriented processor architecture combining producer-ID dataflow issue, block commit/abort, capability-native memory access and a no-speculation design intent.
Source / reference evidenceFrozen executable bootstrap product containing lexer/parser/checker/interpreter, C11 native/FFI, DSIR, formatter/tests/docs/package lock, bootstrap LSP/memory plan and Bible integration.
Source / reference evidenceDigital reliable-link architecture covering CRC integrity, sequencing, retry/replay, parameterized width, lane-fabric hooks and a physical proof top below higher-level GFI/GACF transports.
Source / reference evidenceComposite KOURAN security model combines authority/bounds/rights, epoch revocation, domain isolation, object versioning, replay checks and an external hardened cryptographic boundary.
Source / reference evidenceExecution is driven by continuation tokens rather than SKYRA hyperblocks; a continuation becomes eligible when dependency tokens, authority state and expected object version satisfy the architectural contract.
Source / reference evidenceOne morphable PE lattice is intended to map dense matrix, sparse tensor, vector, reduction, graph and solver/search primitives rather than separate fixed-function dense/sparse islands.
Source / reference evidenceArchitecture or program identity; evaluate scope and implementation status before integration.
Signal, power, thermal/fluidic, mechanical and test/management fabrics under one compiler/evidence model
Architecture IPHierarchical active/passive bridging for local and global package interconnect.
Architecture IPMechanical architecture addressing package expansion and warpage within FPP.
Architecture IPCo-optimizes electrical, power, thermal, mechanical, yield, test and cost constraints
Architecture IPCompute/memory/I/O/power/fabric/management pod + local bridge/RDL + power/thermal/mechanical interfaces
Architecture IPPower-delivery architecture for the FPP multi-physics package platform.
Architecture IP