GIP2

Multi-context authenticated-encryption datapath architecture.

Safety-monitoring island architecture for fault detection, containment and supervised operation; functional-safety certification is not implied.

Mixed Signal — redundant precision BMS ADC subsystem

Automotive CAN controller architecture for message processing, timing and host integration.

Coherent fabric-memory controller architecture with an explicit protocol and physical-interface boundary.

Memory — high-throughput DDR5 controller

Coherent DMA architecture for queued data movement and system integration.

Time-sensitive Ethernet control, queueing and scheduling architecture.

Automotive I/O — 8-channel autonomous LIN controller

Low-power DRAM controller architecture with scheduling and external PHY integration.

AI Compute — 1024 tensor-slice cloud/robotics NPU

AI Compute — 256 tensor-slice edge NPU

PCIe controller and PHY-control integration architecture, with protocol and electrical qualification scoped to the exact release.

Mixed Signal — fractional-N / digitally assisted PLL platform

Security — multi-source silicon PUF root-key subsystem

CPU — high-efficiency RISC-V MCU core

CPU — application-class RISC-V core

CPU — maximum-performance RISC-V core

Memory IP — node-adaptable SRAM compiler architecture

Security — post-quantum-ready root of trust and secure boot

Adaptive serializer/deserializer control architecture; electrical rate and signal-integrity qualification are separate.

Security — side-channel/fault-resistance execution wrapper

AI Compute — format-agnostic sparse tensor accelerator

Security — high-rate multi-entropy TRNG subsystem

AI Compute — dedicated transformer attention/MoE engine

Die-to-die controller architecture for chiplet integration; PHY and standards qualification are release-specific.

USB router and PHY-control architecture with a release-specific compliance and analog boundary.

AI/DSP Compute — 1024-bit deterministic vector DSP